The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also lead to high-k dielectric layers and conductive (e.g., metal) layers being adopted to form gate stacks in various IC devices, such as metal-oxide-semiconductor field-effect-transistors (MOSFETs). The conductive layers are often tuned to have a proper work function to achieve a designed threshold voltage for n-type and p-type devices. Typically, the conductive layers are patterned using a combination of etching processes, for example, dry and wet etching processes. It has been observed that dry etching processes can result in damage to the high-k dielectric and conductive layers; and wet etching processes can result in lateral etching and/or low etching selectivity, degrading patterning profiles. Accordingly, what is needed is an improved method for making an IC device.